Dual Simulation Engines

SiliFlow integrates both Icarus Verilog (iverilog + vvp) and Verilator (verilator), along with automatic sv2v SystemVerilog preprocessing and Slang structural diagnostics.

1. Engine Comparison

Feature	Icarus Verilog (`iverilog` + `vvp`)	Verilator (`verilator`)
Execution Paradigm	Event-driven interpreted simulation	Compiles RTL into high-speed C++ executable
Best For	Behavioral testbenches, rapid iteration, `$display` logs	Cycle-accurate high-throughput SoCs & deep regressions
SystemVerilog Support	Auto-preprocessed via `sv2v` when needed	Native modern SystemVerilog + `--timing` support
Waveform Output	Standard `.vcd` dump discovery	High-speed `.vcd` and trace support

Switch engines anytime from Run → Simulator Engine, Settings (Ctrl+,), the Run & Simulation sidebar, or project.json.

2. Running & Aborting Simulations

Open any RTL file or testbench (e.g., spi_packet_engine_tb.sv).
Optionally pick a specific testbench target under Run → Active Testbench or the Run & Simulation sidebar.
Click Simulate in the top Action Island or press F5.
Click Stop or press Shift+F5 anytime to abort immediately.

3. Watchdog Protection & Pipeline Execution

Under the hood, SiliFlow’s Rust runner orchestrates four stages on asynchronous Tokio background threads so the editor UI stays 100% responsive:

Testbench & RTL Discovery: Classifies workspace RTL vs. testbenches (sim/, tb/, test/, tests/ or _tb / tb_ naming) or follows project.json ordering with -I include dirs and -D defines.
Automatic sv2v Transpilation: If a design uses SystemVerilog features (logic, always_ff, enums, interfaces) while running Icarus Verilog, sv2v preprocesses cleanly in an isolated temp pass.
Configurable Watchdog Timer: Enforces a configurable timeout (120 seconds default, tunable from 10 to 7200 seconds in Settings) so accidental infinite loops (like always #0 clk = ~clk;) never freeze your workstation.
Live Log Streaming & Auto-Load: Compiler/runtime stdout streams directly into the Output panel, diagnostics route to Problems, and generated .vcd / .fst traces load cleanly into the built-in Waveform viewer.