Module Hierarchy Visualizer

Hardware engineers design in nested instance trees rather than flat file lists. SiliFlow builds a live RTL Module Hierarchy Explorer directly inside the left Activity Bar (Ctrl+Shift+H).

1. Automatic Instantiation Tree Construction

HierarchyViewer scans all .v and .sv files across your workspace to construct the complete parent-child design hierarchy:

MODULE HIERARCHY
└── top_soc (top_soc.sv:1)
    ├── u_clk_gen [clk_div] (top_soc.sv:18)
    ├── u_cpu [riscv_mini] (top_soc.sv:32)
    │   ├── u_regfile [regfile_32x32] (riscv_mini.sv:14)
    │   └── u_alu [alu_4bit] (riscv_mini.sv:49)
    └── u_apb_gpio [apb_gpio] (top_soc.sv:71)

• Top-Module Auto-Detection & Override: Automatically detects uninstantiated root modules and testbenches, with a Top-Module dropdown selector when a workspace contains multiple subsystems.
• Missing-Module Indicators: Highlights unresolved sub-module references clearly so broken instantiations are caught before synthesis.
• Search & Tree Controls: Filter deeply nested trees instantaneously and toggle Expand All / Collapse All with one click.

2. Context Menu Actions

Right-click any instance or module node in the Hierarchy Explorer for five targeted actions:

1. Go to Instance: Opens the parent RTL file and scrolls to the exact instantiation line.
2. Go to Definition: Opens the child module’s source file at its module ... header.
3. Copy Hierarchical Path: Copies the dot-separated RTL path (e.g., top_soc.u_cpu.u_alu) for testbench probes and $dumpvars filters.
4. Copy Instantiation: Copies ready-to-paste parameterized module instantiation code.
5. Set as Top Module: Pins the selected module as the workspace root for synthesis, STA, and CDC/RDC analysis.