Smart RTL Code Editor & Split Window

SiliFlow builds on a custom-themed Monaco Studio (siliflow-dark) tailored for Verilog-2001 (IEEE 1364) and SystemVerilog (IEEE 1800-2017) (logic, always_ff, always_comb, always_latch, interface, modport, typedef, enum, struct, package, import, generate).

1. Dual-Pane Split Window (Ctrl+\)

Inspect RTL, testbenches, interfaces, or visualizers side by side without switching tabs:

• Horizontal & Vertical Split: Open Split Right (Ctrl+\) or Split Down via View → Editor Layout, or flip between Side-by-Side / Top-Bottom layouts anytime.
• Open Visualizers to the Side (Alt+Click): Hold Alt while clicking Waveform, FSM, or Schematic in the top Action Island to dock the visualizer directly into the secondary pane.
• Resizable Split Divider: Drag the center divider smoothly (20%–80% clamped, saved per layout) or double-click the divider to reset to 50 / 50.
• Focused Pane Isolation: Focus either pane by clicking or pressing Ctrl+1 / Ctrl+2. Edit actions (Ctrl+S, Ctrl+W, Find/Replace, Comment, Ln/Col telemetry) target the focused pane cleanly.
• Cross-Pane Drag & Drop: Drag tabs to reorder or move across panes with automatic deduplication, synchronized shared file buffers, safe dirty-buffer checks, and automatic single-pane collapse when the secondary pane empties.
• Code-Aware Cross-Probing: Jumping from Problems, Search, Module Hierarchy, Schematic, STA, or CDC automatically focuses a code pane so open Waveform/FSM/Schematic views remain undisturbed.

2. Workspace Symbol Index & F12 Go to Definition

SiliFlow’s background VerilogWorkspaceIndex indexes all .v and .sv files across your project—including unopened files:

• Go to Definition (F12 / Ctrl+Click): Jump across files to module, port, wire, reg, param, task, instance, interface, package, typedef, and class declarations.
• Intelligent Autocomplete (Ctrl+Space): Suggests workspace HDL symbols, ports/parameters with widths and directions, and relative paths inside `include "..." directives.
• Hover Telemetry: Hover over any identifier to inspect signal declaration type, bit vector width, and source file location.
• Built-In ViewState Cache: Cursor position, selections, and scroll offsets stay preserved across tab switches.

3. 350ms Merged Live Linting & STA Overlays

Every edit triggers a debounced 350ms background lint pass combining diagnostics from:

• Icarus Verilog (iverilog)
• Verilator (verilator)
• Slang (slang) (IEEE 1800 SystemVerilog structural diagnostics)

Syntax errors and warnings appear immediately as inline red/yellow squigglies and feed the bottom Problems tab (Ctrl+Shift+M) without clobbering diagnostics from other files.

When Static Timing Analysis runs, SiliFlow also displays inline glowing critical-path line markers and path-hop hover tooltips directly in Monaco and flashes target lines when clicked from the STA panel.

4. Built-In HDL Code Scaffolds (Tools → RTL Code Generators)

Right-click any Verilog/SystemVerilog file in the Explorer or open Tools → RTL Code Generators to scaffold:

• Copy Module Instantiation: Extracts parameters and ports to generate module_name #(...) u_inst (...);.
• Generate Verilog Testbench (.v) or SystemVerilog Testbench (.sv): Scaffolds clock/reset generation, $dumpfile, DUT port bindings, and $finish.
• Generate SystemVerilog Interface (.sv): Emits parameterized interface boilerplate with master and slave modports.
• New From Template (File → New From Template): SystemVerilog Module, Verilog Testbench, SystemVerilog Testbench, SystemVerilog Interface, or project.json.

5. Editor Settings & Shortcuts

Customize ergonomics in Settings (Ctrl+,): Font size (8–32px, default 13px), Tab width (2/4/8), Spaces vs. Tabs, Minimap toggle, and Word Wrap (Alt+Z). Zoom quickly using Ctrl+=, Ctrl+-, and Ctrl+0, search workspace-wide with Ctrl+Shift+F, or middle-click any tab (press and release) to close it.