Regression Suite & Run History

Verifying complex hardware designs requires running suites of unit tests and comparing historical runs. SiliFlow builds both Regression Suite and Run History directly into the bottom panel.

1. Automated Regression Suite Runner

Open the Regression tab in the bottom panel (or via View → Bottom Panels → Regression / Run → Regression Suite):

Automatic Discovery: Finds testbenches declared in project.json alongside workspace testbench patterns (sim/, tb/, _tb, _test, tb_, etc.).
Batch or Single-Test Execution: Click Run Regression Suite to execute every discovered testbench sequentially using either Icarus Verilog or Verilator, run individual suites with Run Single Test, or halt cleanly mid-batch with Stop Suite.
Aggregate Telemetry: Displays overall Pass Rate %, per-test PASS / FAIL badges, execution duration (ms), exit code, inline compiler/assertion error snippets, and a 1-click Open Waveform button per testbench.

Status	Testbench	Engine	Duration	Quick Action
PASS	`spi_packet_engine_tb`	`iverilog`	`42 ms`	Open Waveform
PASS	`alu_4bit_tb`	`verilator`	`18 ms`	Open Waveform
FAIL	`cdc_demo_tb`	`iverilog`	`95 ms`	Inspect Output / Problems

2. Run History Timeline

Every compile and simulation run from F5 or the Run sidebar is logged inside the Run History tab:

Pass/fail status badge and active simulator (iverilog / verilator)
Timestamp and elapsed runtime (ms)
Preserved stdout/stderr console replay
Linked waveform artifact and one-click re-run