Welcome to SiliFlow Studio (v1.2.0)

SiliFlow Studio is a unified, local-first electronic design automation (EDA) desktop workbench built for digital hardware engineers, verification teams, and VLSI students.

Traditional EDA suites force hardware developers across disjointed GUIs, multi-gigabyte installers, brittle FLEXlm license servers, and external waveform popups. SiliFlow brings RTL editing, split-pane navigation, multi-engine compilation & linting, .vcd/.fst waveform analysis, Yosys schematic elaboration, FSM visualization, Static Timing Analysis (STA), CDC/RDC signoff, visual register map codegen, Git history, and an integrated multi-shell terminal together inside one native window.

Key Highlights (v1.2.0)

• Native Tauri v2 + Rust Core: Lightweight installer (under 10 MB), fast native cold start, non-blocking Tokio execution threads, configurable compile/simulation watchdog timer (120s default, 10–7200s), and instant abort (Shift+F5).
• 100% Local-First IP Privacy: Every compile, lint pass, .vcd/.fst parse, netlist elaboration, STA run, CDC/RDC check, Git operation, and register map generation executes directly on your machine—zero cloud uploads.
• Monaco Split-Pane HDL Studio: Dual-pane vertical/horizontal split (Ctrl+\), cross-file F12 Go-to-Definition, 350ms merged diagnostics across Icarus Verilog, Verilator, and Slang, plus inline STA critical-path overlays.
• Dual Simulation & Regression Suite: Run behavioral simulations via Icarus Verilog or cycle-accurate C++ runs via Verilator with automatic sv2v SystemVerilog transpilation, Run History tracking, and automated multi-testbench Regression suites.
• Built-In wellen Waveform Viewer: Stream .vcd and .fst traces up to 100 MB directly in-app with dual measurement cursors (Cursor A / Cursor B, ΔT & derived frequency), HEX / BIN / DEC / OCT radices, scope trees, and signal cross-probing.
• Post-RTL Analysis & Signoff: Interactive Yosys + netlistsvg Gate Schematic with \src cross-probing, automatic FSM Visualizer + Mermaid export, Static Timing Analysis (45nm, 130nm, fpga_lut4, custom .lib), and 5-rule Structural CDC & RDC Explorer.
• Visual Register Map & Git Graph: Design APB / AXI4-Lite / Simple register maps exporting .sv, .h, .rdl, and .md, alongside integrated Git Diff & Visual Commit Graph.

Architecture Overview

┌─────────────────────────────────────────────────────────────────────┐
│                        SILIFLOW STUDIO v1.2.0                       │
├─────────────────────────────────┬───────────────────────────────────┤
│  Monaco Split HDL Editor        │  Integrated Silicon Visualizers   │
│  • Verilog-2001 / SV 2017       │  • wellen VCD / FST Waveforms     │
│  • 350ms Icarus/Verilator/Slang │  • Yosys + netlistsvg Schematics  │
│  • F12 Index & STA Overlays     │  • FSM Graph & Register Map Studio│
├──────────────────┬──────────────┴───────────────────▲───────────────┤
│  Async Rust      │  Tokio IPC & Live Event Streams  │               │
│  Watchdog Runner ▼  (Filesystem Sandbox + SHA-256)  │               │
├─────────────────────────────────────────────────────┴───────────────┤
│                 LOCAL EDA & SIGN-OFF PIPELINE                       │
│  • Simulation & Transpile: iverilog · vvp · verilator · sv2v        │
│  • Lint & Style:           slang · verible                          │
│  • Synthesis & Signoff:    yosys · STA (45nm/130nm/LUT4) · CDC/RDC  │
└─────────────────────────────────────────────────────────────────────┘

System Requirements

Ready to Start?

• Install the app and verify toolchains in Installation & Toolchains.
• Load one of the 8 built-in interactive examples (from Half Adder to RISC-V RV32I and Dual-Clock CDC & RDC Lab) in Getting Started & Workspaces.