Getting Started & Workspaces

SiliFlow Studio adopts familiar desktop IDE ergonomics while keeping hardware project workflows—testbench discovery, dual-pane simulation, STA timing, CDC checks, and schematics—one click away.

1. Opening or Creating a Workspace

When SiliFlow launches (900×600 minimum, 1400×900 default maximized), you can start immediately via:

• Open Folder: Load any local directory of .v, .sv, .svh, or .vh files (File → Open Folder…).
• Open Built-in Demo Project: Loads the bundled Half-Adder starter workspace immediately from Tools → Open Built-in Demo Project or the Welcome screen.
• 8 Built-in Interactive Examples: Launch curated virtual sandbox labs cleanly without creating files on disk first via File → Built-in Examples or Help → Browse Examples Gallery:
  1. Combinational: Half Adder (half_adder.v + half_adder_tb.v)
  2. Combinational: 4-Bit Arithmetic Logic Unit (ALU) (alu_4bit.v + alu_4bit_tb.v)
  3. Sequential: 8-Bit Up/Down Counter with Reset (counter_8bit.v + counter_8bit_tb.v)
  4. State Machines: UART Transmitter FSM (uart_tx.v + uart_tx_tb.v)
  5. State Machines: Traffic Light Controller (traffic_light.v + traffic_light_tb.v)
  6. Bus Peripherals: ARM APB3 Memory-Mapped GPIO Slave (apb_gpio.v + apb_gpio_tb.v)
  7. Advanced SoC: RISC-V RV32I Single-Cycle Mini-Core (riscv_mini.v + riscv_mini_tb.v)
  8. Advanced SoC: Dual-Clock CDC & RDC Lab (cdc_demo.v + cdc_demo_tb.v)
• Clone Repository… (Ctrl+Shift+V): Clone Git repositories directly into a local workspace folder.
• Recent Workspaces: Re-open up to 15 recent workspace folders (File → Open Recent).

2. Project Configuration (project.json)

SiliFlow auto-discovers RTL and testbench files automatically (detecting sim/, tb/, test/, tests/ directories and _tb, _test, _bench, tb_, test_ naming). For complex builds or custom PDK settings, edit project.json via Tools → Edit project.json Configuration or create one via File → New From Template:

{
  "name": "spi_packet_engine",
  "topModule": "spi_packet_engine",
  "sourceFiles": [
    "rtl/spi_packet_engine.sv",
    "tb/spi_packet_engine_tb.sv"
  ],
  "includeDirs": ["include"],
  "defines": ["SIMULATION"],
  "testbenches": [
    {
      "name": "spi_packet_engine_tb",
      "target": "tb/spi_packet_engine_tb.sv",
      "simulator": "iverilog",
      "waveformDump": "waveform.vcd"
    }
  ],
  "flow": {
    "targetPDK": "45nm",
    "clockPeriodNs": 10
  }
}

3. Studio UI Zones & Persistent State

SiliFlow remembers your open tabs, split layout ratio (0.2–0.8), active Activity Bar view, sidebar/bottom panel sizes, settings, and CDC waivers per workspace:

1. Title Bar: File, Edit, Run, View, Tools, Help menus; Quick Open (Ctrl+P); Action Island (Save, Simulate, Waveform, FSM, Schematic — hold Alt+Click on a visualizer to open side-by-side).
2. Activity Bar (Left):
   • Explorer (Ctrl+Shift+E)
   • Search Across Files (Ctrl+Shift+F)
   • Module Hierarchy (Ctrl+Shift+H)
   • Source Control (Git) (Ctrl+Shift+G, shows dirty badge)
   • Run & Simulation
   • Visual Register Map & CSR Codegen
   • Settings (Ctrl+,)
3. Dual-Pane Editor Area: Multi-tab Monaco HDL editor + embedded visualizers (Waveform, Schematic, FSM, Register Map, Diff, Git Graph, and Image Asset Viewer for .png/.svg/.webp).
4. Bottom Panel (8 Tabs): Problems, Output, Terminal, Waveform, Run History, Regression, Timing (STA), and CDC / RDC.
5. Status Bar: Workspace name, Problems error/warning counts, Terminal toggle, Git branch + ahead/behind count, Toolchain status pill, last Simulation verdict (Passed/Failed + ms), Cursor Ln/Col, Spaces/Tab width, UTF-8, and active Language mode.