RTL Schematic Visualizer
Inspect elaborated hardware structure without leaving SiliFlow. The built-in RTL Schematic Visualizer pairs Yosys logic synthesis (with automatic sv2v preprocessing for SystemVerilog) and netlistsvg directly inside an editor tab.
1. Opening the Schematic
- Click Schematic in the top-right Action Island (or
Alt+Clickto dock it in the side split pane beside RTL code). - Press Ctrl+Shift+S.
- Or select Run → Open RTL Schematic.
2. Canvas Controls & Multi-Module Switching
- Zoom & Pan: Drag anywhere to pan across the netlist, scroll to zoom smoothly, or click Zoom In, Zoom Out, and Fit to Screen.
- Fullscreen View: Toggle Fullscreen mode to inspect large multi-stage datapaths edge-to-edge (Esc exits).
- Module Selector: Switch cleanly between top-level and instantiated sub-modules in multi-module designs.
3. Cell Inspector, Resource Telemetry & Cross-Probing
- Cell & Port Inspector: Click any logic gate, DFF, MUX, or I/O port on the schematic to inspect cell type, parameters, connections, and attributes.
- Yosys Resource Statistics (
parseYosysStats): View wire count, wire bits, port count, port bits, total cells, and exact primitive breakdown synthesized by Yosys. - Source Cross-Probing (
\src): SiliFlow parses Yosys\srclocation attributes (file:line) so clicking synthesized cells jumps straight to the originating line in your Verilog/SystemVerilog code pane. - Export
.svg: Download crisp standalone vector SVG netlist diagrams for lab reports, papers, and architecture docs.
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