Terms of Use
These Terms of Use govern your access to and use of SiliFlow's website (siliflow.in) and the SiliFlow Studio desktop application. By downloading, installing, or using SiliFlow, you agree to these terms.
Free for education; straightforward for teams.
SiliFlow is designed to lower the barrier of entry into semiconductor engineering and digital logic design:
100% Free Forever
Students, academic educators, hobbyists, and independent learners are granted a perpetual, royalty-free license to use SiliFlow Studio for learning, teaching, and non-commercial research.
Simple Licensing
Commercial organizations and corporate teams utilizing SiliFlow Studio for revenue-generating silicon products are subject to our simple, seat-based team licensing agreements without license server daemons.
You own your silicon designs completely.
SiliFlow asserts zero intellectual property rights, claims, or royalties over any hardware description files, testbenches, waveforms, gate netlists, or GDSII layout geometries created, edited, or simulated using SiliFlow Studio.
All output generated from your design runs belongs exclusively to you or your organization. SiliFlow will never place restrictive claims or patent encumbrances on your physical silicon tape-outs.
Conditions of use.
When using SiliFlow Studio or accessing our digital infrastructure, you agree not to:
- Attempt to disrupt, overload, or reverse-engineer the web distribution infrastructure of siliflow.in.
- Misrepresent SiliFlow Studio as your own proprietary software for resale or redistribution without explicit written permission.
- Violate the open-source licenses (GPL/LGPL/BSD) of any underlying bundled third-party EDA binaries (e.g. Icarus Verilog or GTKWave).
Silicon tape-out disclaimer.
PLEASE READ CAREFULLY:
SiliFlow Studio is provided “as is” without warranty of any kind, express or implied. Semiconductor design and physical tape-out are inherently complex engineering disciplines.
While SiliFlow strives for precise syntax verification, accurate waveform inspection, and clean toolchain execution, SiliFlow and its founder shall not be held liable for manufacturing costs, foundry mask charges, silicon respins, yield defects, or physical hardware failures resulting from the use of the software. Engineers remain solely responsible for validating their final signoff netlists.
Questions regarding these terms?
For commercial enterprise licensing, academic partnership agreements, or questions regarding these terms, reach out to the founder: