Great chips begin with great tools.
We're building a modern, connected workspace that makes digital hardware design simpler, faster, and more accessible.
SILIFLOW DIRECTContact us
We're here to help with any questions, bug reports, or collaborations. Email us directly at info@siliflow.in or message me on LinkedIn.
Direct Email
info@siliflow.in
Best for technical questions, university workshop setups, bug reports, or commercial licensing inquiries.
Connect with Jignesh Giri
linkedin.com/in/jigneshgiri
Connect on LinkedIn for semiconductor industry networking, VLSI research discussions, academic collaborations, or quick DMs.
Want to help build the modern IDE for silicon?
SiliFlow was born out of frustration with 1990s-era academic EDA rituals. Hardware design should have the speed, polish, and joy of modern software engineering—and we are building this for students and engineers everywhere.
If you have experience or interest in:
- ▸Rust async backends & process orchestration
- ▸Tauri v2 desktop architecture
- ▸Monaco Editor & SystemVerilog LSP / Slang
- ▸Interactive canvas waveform renderers (VCD / FST)
- ▸Yosys synthesis, STA & CDC/RDC engines
- ▸Writing tutorials & RTL lab examples
Found a bug? Help us break the tool so we can fix it.
If you encountered a simulator crash, SystemVerilog parsing quirk, or waveform artifact, use the form at the top of this page or send an email directly.
- 1. Operating System: Windows 10/11, macOS (Intel/Apple Silicon), or Linux distro
- 2. RTL Snippet: Minimal Verilog / SystemVerilog code that triggers the issue
- 3. Observed vs Expected: What happened vs what should have happened
- 4. Screenshot / Log: Any terminal, Output console, or Problems error message