01 — WAVEFORMSSILIFLOW
Built-in .vcd & .fst waveform viewer
Native Rust wellen engine parses VCD and FST traces up to 100 MB with hierarchy scopes, HEX/BIN/DEC/OCT radices, Cursor A/B delta & frequency math, and X/Z hazard colors.
The desktop IDE formodern silicon design
Native desktop IDE for RTL simulation, Yosys synthesis, STA timing, CDC/RDC checks, and gate schematics — 100% local on your machine.
v1.2Explore Live Flow & Roadmap
No license servers. No six-week setup. Built as a compiled native desktop studio that launches in milliseconds, stays offline by default, and replaces legacy toolchains on Windows, macOS, and Linux.
QFN-28 · SILIFLOW DIE 01X:158µm · Y:158µm
HOVER OR CLICK ANY DIE QUADRANT TO TRACE SIGNAL & TELEMETRY
BENCHMARK DATASHEET236× FASTER
Native Cold Start
180 msCompiled native Tauri v2 and Rust desktop runtime opens directly into your workspace without heavyweight virtual machines or display forwarding.
SILIFLOW STUDIO NATIVE180 ms
LEGACY VENDOR SUITES42.5 s legacy JVM / X11
0|50%|42.5 s
WINDOWSLINUXMACOS
SIM ▸ IVERILOG + VERILATORWAVEFORMS ▸ VCD + FST (100 MB)SYNTH & SCHEMATIC ▸ LIVESTA TIMING ▸ 45nm / 130nm / .LIBCDC & RDC MATRIX ▸ LIVELINT ▸ 350ms SLANG + VERILATORSPLIT EDITOR ▸ CTRL+\REGMAP STUDIO ▸ APB / AXI4-LITEGIT GRAPH + TERMINAL ▸ LIVETOOLS DETECTED ▸ 8SANDBOX EXAMPLES ▸ 8STARTUP ▸ 180 msFREE FOR LEARNERS ▸ YESLICENSE SERVERS ▸ 0SIM ▸ IVERILOG + VERILATORWAVEFORMS ▸ VCD + FST (100 MB)SYNTH & SCHEMATIC ▸ LIVESTA TIMING ▸ 45nm / 130nm / .LIBCDC & RDC MATRIX ▸ LIVELINT ▸ 350ms SLANG + VERILATORSPLIT EDITOR ▸ CTRL+\REGMAP STUDIO ▸ APB / AXI4-LITEGIT GRAPH + TERMINAL ▸ LIVETOOLS DETECTED ▸ 8SANDBOX EXAMPLES ▸ 8STARTUP ▸ 180 msFREE FOR LEARNERS ▸ YESLICENSE SERVERS ▸ 0
Eight stages. One flow. Five core stages live in Studio v1.2 — simulation, Yosys synthesis, lint & CDC, RDC, and STA timing — with DFT, formal, and GDSII on the open roadmap.
01LIVE
Simulate
Icarus Verilog & Verilator with auto sv2v, Regression Suite, and Run History.
02LIVE
Synthesize
Yosys netlist elaboration, interactive gate schematics, cell stats & SVG export.
03LIVE
Lint & CDC
350ms multi-engine lint (Icarus, Verilator, Slang) plus 5-rule Yosys CDC matrix.
04LIVE
RDC
Structural asynchronous reset-domain crossing checks with matrix filters & waivers.
05PLANNED
DFT
Scan insertion and coverage in the same flow.
06LIVE
STA
45nm, 130nm, fpga_lut4, or custom .lib slack, Fmax & inline RTL path highlights.
07PLANNED
Formal
Equivalence checks stitched between stages.
08DESTINATION
GDS2
Physical silicon layout ready for the fab on the open roadmap.
The clarity that mere logs cannot buy. From sub-second simulation and FST waveforms to Yosys synthesis, STA critical paths, CDC matrices, and CSR codegen — every verdict lives inside one editor.
02 — FSM GRAPHSILIFLOW
Automatic FSM visualizer
Extracts state enums and transitions directly from SystemVerilog/Verilog source with reset state highlighting, multi-FSM switching, and 1-click Mermaid stateDiagram-v2 export.
03 — SCHEMATICSILIFLOW
Yosys interactive gate schematic
Synthesize RTL into netlist schematics inside an editor tab (auto sv2v) with gate/pin inspection, Yosys resource breakdown, \src RTL cross-probing, and standalone SVG export.
sta + cdc45nm · YOSYS
SLACK (45nm)+1.84 ns MET
MAX FREQ316.4 MHz
CDC / RDCSAFE_2FF_SYNC
Path: u_alu/carry_reg → out_q4 gate hops
CDC Matrix: clk_a × clk_b1 waiver · async_rst checked
04 — TIMING & CDCSILIFLOW
STA timing & CDC/RDC signoff
Analyze setup slack and Fmax across 45nm, 130nm, fpga_lut4, or custom .lib libraries with glowing inline Monaco path highlights, plus a 5-rule Yosys CDC/RDC matrix and waivers.
Ctrl+\ splitF12 · SLANG LINT
rtl/uart_tx.svLINT ✓
typedef enum logic [1:0] { IDLE, START, DATA} state_t;always_ff @(posedge clk) state <= next_state;// F12 → port definition
tb/uart_tx_tb.svPANE 2
`include "rtl/uart_tx.sv"uart_tx #(.BAUD(115200)) dut (.clk(clk), ...);initial $dumpfile("w.fst");assert (tx_done == 1'b1);// synced buffer + view
05 — SPLIT EDITORSILIFLOW
Dual-pane split IDE & F12 index
Split horizontally or vertically (Ctrl+\), drag tabs across panes, Alt+Click visualizers to the side, jump cross-file with F12 Go-to-Definition, and get 350ms merged lint diagnostics.
regmap.rdlAPB · AXI4-LITE
0x00CTRL_REG
[3:0] en, modeRW
0x04STATUS
[0] busy, [1] doneRO
0x08IRQ_FLAG
[7:0] tx_done_irqW1C
↗ rtl_slave.sv↗ regs.h↗ map.rdl↗ docs.md
06 — REGISTER MAPSILIFLOW
Visual Register Map & CSR Codegen
Configure APB, AXI4-Lite, and Simple peripherals (RW, RO, WO, W1C) with offset/overlap validation and export synced SystemVerilog RTL, C headers, SystemRDL (.rdl), and Markdown docs.
regression + git100% PASS
Suite: spi + uart + riscv_mini100% PASS (8/8)
iverilog + verilator · Run Historyavg 164 ms
main· git commit graph ↑1
PowerShell · Bash07 — REGRESSION & GITSILIFLOW
Regression Suite, Git Graph & Terminal
Run all workspace testbenches with Icarus or Verilator for pass-rate & ms latency telemetry, inspect visual Git commit graphs and diffs, and launch multi-shell terminals inline.
tools/8 LOCAL BINARIES
iverilog
vvp
gtkwave
sv2v
verilator
yosys
verible
slang
Tauri v2 + Rust Tokio · SHA-256 Managed Installer
● 100% LOCAL EXECUTION — 0 BYTES UPLOADED08 — LOCAL CORESILIFLOW
Tauri v2 native · 8 detected EDA tools
Auto-detects iverilog, vvp, gtkwave, sv2v, verilator, yosys, verible, and slang locally (with a 1-click SHA-256 managed Windows installer). 0 bytes of your RTL ever leave disk.
Stop renting licenses. Legacy suites quote, expire, and lock students out. SiliFlow stays free for learners and straightforward for hardware teams.
01 · ACCESSIBLE
Free to learn, plain to license
No dongles, no segment keys, no IT queue — SiliFlow is free for students, hobbyists and anyone learning the craft. Companies pay one simple license and install in the same minute.
02 · UNIFIED FLOW
One flow, not six vendors
Dual-engine simulation, Yosys schematics, STA timing, CDC/RDC checks, and CSR generation share one project and one UI — DFT, formal, and GDSII follow next.
03 · LOCAL FIRST
Runs on your desk
Your RTL, waveforms, and netlists never upload. Built on Tauri v2 + Rust Tokio for Windows, Linux, and macOS with non-blocking execution and instant abort.
Made with SiliFlow. Launch 8 built-in interactive examples — from Half Adder and UART FSM to RISC-V RV32I, APB3 GPIO, and Dual-Clock CDC labs.
SYNTHESIZED RTL▷
SPI packet engine
29 COMPONENTS · PASSED IN 210ms
8 BUILT-IN EXAMPLES▷
RISC-V RV32I & APB3 GPIO
SANDBOX GALLERY · NO FOLDER NEEDED
DUAL-CLOCK LAB▷
CDC & RDC timing suite
5 STRUCTURAL RULES + 45nm STA
Built for real silicon.
Download SiliFlow Studio v1.2.
Icarus & Verilator simulation, VCD/FST waves, Yosys schematics, STA timing, CDC/RDC signoff, and Git in one native window. Free forever for students.
WINDOWS
DESKTOP STUDIO
Installer (.exe / .msi)
Windows 10 / 11 · 64-bit
1-click SHA-256 managed tools · Zero PATH edits required
Download for Windows
Siliflow-Setup-x64.exe
MACOS
DESKTOP STUDIO
Apple Disk Image (.dmg)
Apple Silicon (M-series) & Intel
Native ARM64 & x86_64 · Auto-detects 8 local EDA engines
Download for macOS
Siliflow-Universal.dmg
LINUX
DESKTOP STUDIO
Portable (.AppImage / .deb)
x86_64 · Ubuntu, Fedora, Debian, Arch
Self-contained Tauri v2 studio · Built-in terminal & Git
Download for Linux
Siliflow-x86_64.AppImage
✓ NO LICENSE SERVERS · NO ADMIN ACCESS · UNDER 100 MBSTUDENTS & EDUCATORS: 100% FREE